1. Field
The present embodiments relate to a liquid crystal display.
2. Related Art
Generally, a liquid crystal display controls light transmittance of liquid crystal cells in accordance with video signals to thereby display a picture. An active matrix type of liquid crystal display having a switching device provided for each liquid crystal cell moves the picture by permitting an active control of the switching device. The switching device used for the active matrix liquid crystal display mainly employs a thin film transistor (hereinafter, referred to as “TFT”) as shown in FIG. 1.
Referring to FIG. 1, the active matrix LCD converts a digital input data into an analog data voltage on the basis of a gamma reference voltage and supplies it to a data line DL. At the same time, the active matrix LCD supplies a scanning pulse to a gate line GL to thereby charge a liquid crystal cell Clc.
A gate electrode of the TFT is connected to the gate line GL while a source electrode thereof is connected to the data line DL. A drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and to one electrode of a storage capacitor Cst.
A common electrode of the liquid crystal cell Clc is supplied with a common voltage Vcom.
The storage capacitor Cst charges a data voltage fed from the data line DL when the TFT is turned-on, thereby constantly maintaining a voltage at the liquid crystal cell Clc.
If the scanning pulse is applied to the gate line GL, then the TFT is turned on to provide a channel between the source electrode and the drain electrode thereof, thereby supplying a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc. Liquid crystal molecules of the liquid crystal cell have an alignment changed by an electric field between the pixel electrode and the common electrode to thereby modulate an incident light.
FIG. 2 is a block diagram showing a configuration of a related art liquid crystal display.
Referring to FIG. 2, the related art liquid crystal display 100 includes a liquid crystal display panel 110 provided with a thin film transistor (TFT) driving the liquid crystal cell Clc at an intersection of data lines DL1 to DLm and gate lines GL1 to GLn crossing each other. A data driver 120 supplies data to the data lines DL1 to DLm of the liquid crystal display panel 110. A gate driver 130 supplies a scanning pulse to the gate lines GL1 to GLn of the liquid crystal display panel 110. A gamma reference voltage generator 140 generates a gamma reference voltage and supplies it to the data driver 120. A backlight assembly 150 irradiates a light onto the liquid crystal display panel 110. An inverter 160 applies an alternating current voltage and a current to the backlight assembly 150. A common voltage generator 170 generates a common voltage Vcom to supply it to the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110. A gate driving voltage generator 180 generates a gate high voltage VGH and a gate low voltage VGL and supplies them to the gate driver 130. A timing controller 190 controls the data driver 120 and the gate driver 130.
The liquid crystal display panel 110 has a liquid crystal injected between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn perpendicularly cross each other. Each intersection between the data lines DL1 to DLm and the gate lines GL1 to GLn is provided with the TFT. The TFT supplies a data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scanning pulse. The gate electrode of the TFT is connected to the gate lines GL1 to GLn while the source electrode thereof is connected to the data line DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and to the storage capacitor Cst.
The TFT is turned-on in response to the scanning pulse applied, via the gate lines GL1 to GLn, to the gate terminal thereof. Upon turning-on of the TFT, a video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.
The data driver 120 supplies data to the data lines DL1 to DLm in response to a data driving control signal DDC supplied from the timing controller 190. The data driver 120 samples and latches a digital video data RGB fed from the timing controller 190, and then converts it into an analog data voltage capable of expressing a gray scale level at the liquid crystal cell Clc of the liquid crystal display panel 110 on the basis of a gamma reference voltage from the gamma reference voltage generator 140, thereby supplying it to the data lines DL1 to DLm.
The gate driver 130 sequentially generates a scanning pulse, for example, a gate pulse in response to a gate driving control signal GDC and a gate shift clock GSC supplied from the timing controller 190 to supply them to the gate lines GL1 to GLn. The gate driver 130 determines a high level voltage and a low level voltage of the scanning pulse in accordance with the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 180.
The gamma reference voltage generator 140 is supplied with a power supply voltage of 0V to 3.3V supplied from a system mounted on the liquid crystal display 100, for example, a controller (not shown) of an image display apparatus such as a TV set to generate a positive gamma reference voltage and a negative gamma reference voltage and output them to the data driver 120.
The backlight assembly 150 is provided at the rear side of the liquid crystal display panel 110, and is radiated by an alternating current voltage and a current supplied from the inverter 160 to irradiate a light onto each pixel of the liquid crystal display panel 110.
The inverter 160 converts a square wave signal generated at the interior thereof into a triangular wave signal. The inverter 160 compares the triangular wave signal with a direct current power voltage VCC supplied from said system, thereby generating a burst dimming signal proportional to a result of the comparison. If the burst dimming signal determined in accordance with the rectangular wave signal at the interior of the inverter 160, then a driving integrated circuit (IC) (not shown) that controls a generation of the AC voltage and current within the inverter 160 controls a generation of AC voltage and current supplied to the backlight assembly 150 in response to the burst dimming signal.
The common voltage generator 170 receives a power supply voltage VCC from the system to generate a common voltage Vcom, and supplies it to the common electrode of the liquid crystal cell Clc provided at each pixel of the liquid crystal display panel 110.
The gate driving voltage generator 180 is supplied with a power supply voltage VCC of 3.3V supplied from the system to generate the gate high voltage VGH and the gate low voltage VGL, and supplies them to the gate driver 130. The gate driving voltage generator 180 generates a gate high voltage VGH more than a threshold voltage of the TFT provided at each pixel of the liquid crystal display panel 110 and a gate low voltage VGL less then the threshold voltage of the TFT. The gate high voltage VGH and the gate low voltage VGL generated in this manner are used to determine a high level voltage and a low level voltage of the scanning pulse generated by the gate driver 130, respectively.
The timing controller 190 supplies a digital video data RGB supplied from a digital video card (not shown) to the data driver 120, and generates a data driving control signal DDC and a gate driving control signal GDC using horizontal/vertical synchronization signals H and V in response to a clock signal CLK and supplies them to the data driver 120 and the gate driver 130, respectively. The data driving control signal DDC includes, for example, a source shift clock SSC, a source start pulse SSP, a polarity control signal POL and a source output enable signal SOE. The gate driving control signal GDC includes, for example, a gate start pulse GSP and a gate output enable signal GOE.
A structure of a color filter provided at a related art liquid crystal display having such a configuration and function will be described with reference to FIG. 3A to FIG. 3C.
FIG. 3A is a structure chart of a color filter of a related art liquid crystal display, and exemplarily shows a structure of RGB color filters of each pixel provided on the liquid crystal display panel 110.
Referring to FIG. 3A, one of RGB color filters is formed at a plurality of pixels provided on the liquid crystal display panel 110, respectively. Such a pixel is comprised of three sub-pixels, for example, an R color filter, a G color filter and a B color filter. A thin film transistor TFT corresponds to each color filter formed on three sub-pixels.
FIG. 3B is a structure chart of a color filter of a related art liquid crystal display, and exemplarily shows a structure of a RGB/C color filter of each pixel provided on the liquid crystal display panel 110.
Referring to FIG. 3B, one RGB/C color filter is formed at a plurality of pixels provided on the liquid crystal display panel 110, respectively. Such a pixel is comprised of four sub-pixels, for example, an R color filter, a G color filter, a B color filter and a C color filter. A thin film transistor TFT corresponds to each color filter formed on four sub-pixels.
FIG. 3C is a structure chart of a color filter of a related art liquid crystal display, and exemplarily shows a structure of RGB/CMY color filters of each pixel provided on the liquid crystal display panel 110.
Referring to FIG. 3C, one of RGB/CMY color filters is formed at a plurality of pixels provided on the liquid crystal display panel 110, respectively. Such a pixel is comprised of six sub-pixels, for example, an R color filter, a G color filter, a B color filter, a C color filter, an M color filter and a Y color filter. A thin film transistor TFT corresponds to each color filter formed on six sub-pixels.
As described above, if RGB/C color filters or RGB/CMY color filters are used at a related art liquid crystal display, then four color filters or six color filters are formed at one pixel. The number of thin film transistor used at each pixel is increased. For example, if a RGB/C color filter is used, then four thin film transistors are formed in such a manner to correspond to each color filter at one pixel, and if RGB/CMY color filters are used, then six thin film transistors are formed in such a manner to correspond to each color filter at one pixel. As a result, an aperture ratio of each pixel is reduced in proportion to the number of thin film transistor, so that the brightness is reduced.
The present embodiments are related to an liquid crystal display. The present embodiments may obviate one or more of the limitations of the related art. For example, in one embodiment, a liquid crystal display separates and forms RGB color filters and CMY color filters at different pixels so that the brightness of each pixel is not reduced. In another example, in one embodiment the number of thin film transistors provided at each pixel is reduced, so that the aperture ratio of each pixel is increased.
In one embodiment, a liquid crystal display according comprises a liquid crystal display panel formed of a plurality of first pixels provided with RGB color filters and a plurality of second pixels provided with CMY color filters. A video processing part is inputted with RGB data to generate CMY data, and selectively outputs the RGB data in accordance with a clock signal and CMY data generated in accordance with a clock signal. A control part controls a supply of RGB data or CMY data inputted from the video processing part in accordance with the clock signal. A data driving part converts RGB data outputted from the control part or CMY data into an analog data in accordance with a control of the control part, and supplies it to the plurality of first pixel or the plurality of second pixel.
The video processing part includes a data processor that inputs RGB data to generate CMY data and to output RGB data and CMY data. A data supply controller controls a supply of RGB data and CMY data outputted from the data processor in accordance with the clock signal. A data selector selects RGB data or CMY data that is inputted from the data processor in accordance with a control of the data supply controller to output it to the control part.
In one embodiment of the liquid crystal display, the data processor generates a C data using a G data and a B data.
In one embodiment of the liquid crystal display, the data processor generates an M data using an R data and a B data.
In one embodiment of the liquid crystal display, the data processor generates a Y data using an R data and a G data.
In one embodiment, the data selector includes a first multiplexer that selects a R data inputted from the data processor or a C data in accordance with a control of the data supply controller to output it to the control part. A second multiplexer selects a G data or an M data inputted from the data processor in accordance with a control of the data supply controller to output it to the control part. A third multiplexer selects a B data or a Y data inputted from the data processor in accordance with a control of the data supply controller to output it to the control part.
In one embodiment of the liquid crystal display, if a low-level supply control signal is inputted from the data supply controller, then the first multiplexer selects and outputs a R data. In another embodiment, if a high-level supply control signal is inputted from the data supply controller, then the first multiplexer selects and outputs a C data.
In one embodiment of the liquid crystal display, if a low-level supply control signal is inputted from the data supply controller, then the second multiplexer selects and outputs a G data. In another embodiment, if a high-level supply control signal is inputted from the data supply controller, then the second multiplexer selects and outputs an M data.
In one embodiment of the liquid crystal display, if a low-level supply control signal is inputted from the data supply controller, then the third multiplexer selects and outputs a B data. In another embodiment, if a high-level supply control signal is inputted from the data supply controller, then the third multiplexer selects and outputs a Y data.